The present invention generally relates to semiconductor devices and more particularly to the formation of an alignment mark on a semiconductor device for establishing an alignment of the semiconductor device with respect to a mask carrying a semiconductor pattern at the time of patterning.
The technique of multi-level interconnection is used commonly for increasing the integration density of integrated circuits. In a typical multi-level interconnection structure, a plurality of conductor layers are provided with an insulator layer provided therebetween. Contacts with the semiconductor device or contacts between the conductor layers of different levels are made by providing contact holes through the insulator layer.
FIG. 1 shows a cross-section of a typical prior art contact hole. Referring to FIG. 1, a part of a substrate or wafer 11, which may be a part of the semiconductor device formed within the substrate 11, is electrically connected to, an aluminum layer 13 via a contact hole 14 provided in an insulator layer 12 which is sandwiched between the substrate 11 and the aluminum layer 13. In the actual process of forming the structure of FIG. 1, the contact hole 14 is formed in the insulator layer 12 and the aluminum layer 13 is deposited on the insulator layer 12 including the contact hole 14 by sputtering. In such a structure, it is known that there is formed an overhang structure in the aluminum layer 13 in correspondence to the top part of the contact hole 14 as can be seen in the drawing. As a result of the formation of the overhang structure, the deposition of aluminum on the side wall of the contact hole is obstructed and there is a tendency that the aluminum layer 13 has a reduced thickness particularly at the bottom part of the side wall of the contact hole. Such a thin conductor part in the contact hole invites concentration of current which in turn tends to cause a failure of electric connection due to the electromigration effect.
In order to eliminate the formation of the overhang structure, use of bias sputtering has been proposed recently for deposition of the aluminum layer 13. According to this technique, the deposition of aluminum is made by applying an acceleration voltage as well as by heating of the substrate. As a result, the contact hole 14 is filled substantially completely with the aluminum layer 13 as shown in FIG. 2 and the foregoing problem of unreliable electrical contact is eliminated.
Meanwhile, in the fabrication of a semiconductor device on a semiconductor wafer, it is commonly practiced to provide one or more alignment marks on the wafer so that an exact alignment is achieved between the mask and the wafer at the time of patterning.
FIG. 3 shows a typical semiconductor wafer 11 on which a number of semiconductor devices 15 are formed. These semiconductor devices 15 are separated from each other on the wafer 11 by a number of scribe lines or dicing lines 16, and a number of alignment marks 17 are formed in correspondence to the dicing lines 16 so as to achieve the alignment between the wafer 11 and the mask (not shown) at the time of transferring the pattern of the semiconductor device carried by the mask on the wafer 11. These alignment marks 17 are formed generally as holes or depressions provided in correspondence to the dicing lines 16.
When the bias sputtering technique described previously is applied for depositing aluminum or other conductors on the semiconductor device 15 for multi-level interconnection, there arises a problem in that the alignment marks 17 are filled more or less completely with the deposited conductor and the detection of the marks 17 becomes difficult. When the detection of the alignment marks 17 is made erroneously or not made at all, the process of forming a new pattern on the previously patterned semiconductor device with exact alignment becomes impossible. In order to avoid this problem, it is conventionally practiced to provide the alignment marks 17 after the deposition of the conductor layer by the bias sputtering. However, such an extra step increases the number of steps in the fabrication of the semiconductor device and hence increases the cost of the semiconductor device. It should be noted that such an additional formation of the alignment mark has to be made each time a new conductor layer is provided and thus, this problem of increasing the number of steps is particularly serious when fabricating a semiconductor device having a multi-level interconnection structure.